In certain prior art phase lock loop circuits, a voltage controlled oscillator generates a local reference signal having a frequency which is substantially that of the signal to be received. The local reference signal is varied in phase in response to the voltage level of a control signal that is applied to the voltage controlled oscillator. The control signal is a function of the difference between the phasing of the received signal and the phasing of the local reference signal. The control signal can be derived in a number of ways, one of which is to utilize an up-and-down counter which will produce a resultant positive or negative count that is proportional to the lead or lag of the phase of the received signal with respect to the locally generated reference signal.
One prior art system which is of interest for its teaching of a phase lock circuit wherein both phase and frequency is adjusted is disclosed in U.S. Pat. No. 3,646,452, entitled "Second Order Digital Phase-Lock Loop", by Isaac Horowitz. The system disclosed in the referenced patent is digital in nature.
Another prior art system of interest is disclosed in U.S. Pat. No. 3,781,695, entitled "Digital Phase Locked Loop", by Edward J. Jackson, wherein a reference oscillator of fixed frequency has derived from it the required reference signal by utilizing an up-down counter which is incremented or decremented as a function of the difference between the lead or lag of the phase of the received signal in relation to the phase of the fixed frequency signal. The output signal from the reference oscillator and the output from the up-down counter are directed to a divider circuit wherein the inputs are divided by a consistent K resulting in the addition or subtraction of a pulse into the output signal from the divider, depending upon whether the counter was up or down.